? semiconductor components industries, llc, 2003 october, 2003 ? rev. 2 23 publication order number: mc100e210/d mc100e210 5vecl dual 1:4, 1:5 differential fanout buffer the mc100e210 is a low voltage, low skew dual differential ecl fanout buffer designed with clock distribution in mind. the device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. the device features fully differential clock paths to minimize both device and system skew. the dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part?to?part skew down to an output?to?output skew. this capability reduces the skew by a factor of 4 as compared to using two lve111's to accomplish the same task. the lowest tpd delay time results from terminating only one output pair, and the greatest tpd delay time results from terminating all the output pairs. this shift is about 10?20 ps in tpd. the skew between any two output pairs within a device is typically about 25 ns. if other output pairs are not terminated, the lowest tpd delay time results from both output pairs and the skew is typically 25 ns. when all outputs are terminated, the greatest tpd (delay time) occurs and all outputs display about the same 10?20 ps increase in tpd, so the relative skew between any two output pairs remains about 25 ns. for more information on using pecl, designers should refer to application note an1406/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? dual differential fanout buffers ? 200 ps part?to?part skew ? 50 ps typical output?to?output skew ? low voltage ecl/pecl compatible ? the 100 series contains temperature compensation ? 28?lead plcc packaging ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?4.2 v to ?5.7 v ? internal input 75 k pulldown resistors ? q output will default low with inputs open or at v ee ? esd protection: human body model; >2 kv, machine model; >200 v ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul 94 v?0 @ 0.125 in, oxygen index: 28 to 34 ? transistor count = 179 devices device package shipping 2 ordering information *for additional information, see application note and8002/d mc100e210fn plcc?28 37 units / rail mc100e210fnr2 plcc?28 500 tape & reel marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc?28 fn suffix case 776 mc100e210fn awlyyww 128 http://onsemi.com 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
mc100e210 http://onsemi.com 24 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 v ee v bb clka v cc clka clkb clkb qa3 qa3 qb0 v cco qb0 qb1 qb1 28?lead plcc (top view) qa0 qa0 qa1 v cco qa1 qa2 qa2 qb4 qb3 qb2 qb4 v cco qb3 qb2 pin description function ecl differential input pairs ecl differential input pairs ecl differential outputs ecl differential outputs reference output voltage positive supply negative supply pin clka, clkb clka , clkb qa0:3, qb0:4 qa0:3 , qb0:4 v bb v cc, v cco v ee logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. qb4 qb4 logic symbol qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 v bb clka clka qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 clkb clkb maximum ratings (note 1) symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v ?8 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range 0 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w jc thermal resistance (junction?to?case) standard board 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 ?5.7 to ?4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100e210 http://onsemi.com 25 pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 2) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 55 65 ma v oh output high voltage (note 3) 3915 3995 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 3) 3170 3305 3445 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (single?ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mv v il input low voltage (single?ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 4) 2.7 4.6 2.7 4.6 2.7 4.6 v i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary ?0.46 v / +0.8 v. 3. outputs are terminated through a 50 resistor to v cc ? 2 volts. 4. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . necl dc characteristics v ccx = 0.0 v; v ee = ?5.0 v (note 5) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 55 65 ma v oh output high voltage (note 6) ?1085 ?1005 ?880 ?1025 ?950 ?880 ?1025 ?950 ?880 mv v ol output low voltage (note 6) ?1830 ?1695 ?1555 ?1810 ?1745 ?1620 ?1810 ?1740 ?1620 mv v ih input high voltage (single?ended) ?1165 ?1025 ?880 ?1165 ?1025 ?880 ?1165 ?1025 ?880 mv v il input low voltage (single?ended) ?1810 ?1645 ?1475 ?1810 ?1645 ?1475 ?1810 ?1645 ?1475 mv v bb output voltage reference ?1.38 ?1.26 ?1.38 ?1.26 ?1.38 ?1.26 v v ihcmr input high voltage common mode range (differential configuration) (note 7) ?2.3 ?0.4 ?2.3 ?0.4 ?2.3 ?0.4 v i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. input and output parameters vary 1:1 with v cc . v ee can vary ?0.46 v / +0.8 v. 6. outputs are terminated through a 50 resistor to v cc ? 2 volts. 7. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc100e210 http://onsemi.com 26 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = ?5.0 v (note 8) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 700 700 700 mhz t plh t phl propagation delay to output in (differential) (note 9) in (single?ended) (note 10) 475 400 675 700 500 450 700 750 500 450 700 750 ps t skew within?device skew qa to qb qa to qa,qb to qb part?to?part skew (differential) (note 11) 50 50 75 75 200 50 30 75 50 200 50 30 75 50 200 ps t jitter random clock jitter (rms) < 1 < 1 < 1 ps v pp input voltage swing (differential configuration) (note 12) 500 500 500 mv t r / t f output rise/fall time (20%?80%) 200 600 200 600 200 600 ps 8. v ee can vary ?0.46 v / +0.8 v. 9. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the ou tput signal. 11. the within?device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. v pp (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the e210 as a differential input as low as 50 mv will still produce full ecl levels at the output.
mc100e210 http://onsemi.com 27 figure 3. typical termination for output driver and device evaluation (see application note and8020 ? termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc ? 2.0 v resource reference of application notes an1404 ? eclinps circuit performance at non?standard v ih levels an1405 ? ecl clock distribution techniques an1406 ? designing with pecl (ecl at +5.0 v) an1503 ? eclinps i/o spice modeling kit an1504 ? metastability and the eclinps family an1568 ? interfacing between lvds and ecl an1596 ? eclinps lite translator elt family spice i/o model kit an1650 ? using wire?or ties in eclinps designs an1672 ? the ecl translator guide and8001 ? odd number counters design and8002 ? marking and date codes and8020 ? termination of ecl logic devices
|
